1. Field of the Invention
This invention relates to computer systems and more particularly to arbitration mechanisms for determining and prioritizing ownership of a bus among several masters in a computer system.
2. Description of the Relevant Art
Computer architectures generally include a plurality of devices interconnected by one or more buses. For example, conventional computer systems typically include a CPU coupled through bridge logic to a main memory. The bridge logic also typically couples to a high bandwidth local expansion bus, such as the Peripheral Component Interconnect (PCI) bus or the VESA (Video Electronics Standards Association) VL bus. Modern local bus standards such as the PCI bus and the VL bus are not constrained by a requirement to be backwards compatible with prior expansion bus adapters and thus provide much higher throughput than older expansion buses. Examples of devices which can be coupled to local expansion buses include SCSI adapters, network interface cards, video accelerators, audio cards, telephony cards, etc. An older-style expansion bus may also be coupled to the local expansion bus to provide compatibility with earlier-version expansion bus adapters. Examples of such expansion buses include the industry standard architecture (ISA) bus, also referred to as the AT bus, the extended industry standard architecture (EISA) bus, and the microchannel architecture (MCA) bus. Various devices may be coupled to this second expansion bus, including a fax/modem, sound card, etc.
When two or more masters reside on a particular bus, arbitration logic is typically required to determine and prioritize ownership of the bus. For example, a CPU local bus arbiter as well as a PCI bus arbiter are typically included as part of the bridge logic in many computer systems. In the PCI bus architecture each bus master has two unique side band signals for master arbitration. These signals are REQ (request for mastership) and GNT (granted mastership). The CPU local bus arbiter within a typical computer system determines and prioritizes ownership of the CPU local bus, while the PCI bus arbiter determines and prioritizes ownership of the PCI bus. Mastership of either bus is typically based on a fixed arbitration fairness scheme, such as a round-robin algorithm. The arbitration scheme is typically not based upon the status of the target devices for which access is sought, nor upon the type of cycle the master plans to initiate. Thus, the arbiter may grant ownership of the bus even though the requesting master is attempting to access a target resource which is unavailable to accommodate the data transfer. In such situations, a target termination retry cycle or an abort cycle must be initiated, and the master must wait until a later time to perform its desired operation.
It is common in high performance embedded controller applications for the controller to act as a bus master. Exemplary embedded controllers include disk array controllers and network interface controllers. In an embedded controller, a central arbiter typically controls each master's request REQ/GNT handshake and, similar to the previous discussion, prioritizes mastership of the controller's local busses based on an arbitration fairness scheme. The central arbiter is usually an integral part of the host memory controller interface and may have knowledge of the PCI to memory buffer status. However, the arbiter will grant a requesting master bus ownership without knowledge of the specific bus cycle the master plans to initiate. Again, a target termination retry cycle or an abort cycle may be required if the target resource to be accessed is unavailable when the arbiter grants ownership of the bus.
For example, consider a situation within an embedded controller wherein two PCI bus masters are requesting bus ownership simultaneously. One of the masters plans to effectuate a memory read, and the other master plans to effectuate a memory write. For this example, it is assumed that the PCI memory controller's prefetch buffer is not empty (i.e., it contains data that is targeted to another PCI device) and that the write posting buffer is empty. If the central arbiter grants ownership to the master who plans to do a memory read first based purely on a fairness algorithm, the master will initiate the memory read only to be stopped via a PCI target termination retry cycle by the memory target since the prefetch buffer is not empty. The occurrence of such operations may significantly degrade bus bandwidth and may therefore undesirably affect the overall performance of the computer system.